1. Field of the Invention
The present invention relates to an error correction coding/decoding technology. The present invention particularly relates to a coding apparatus and a decoding apparatus for performing error correction coding/decoding on data stored in a storage medium, an amplitude adjustment apparatus, a recorded information reader, a signal processing apparatus and a storage system.
2. Description of the Related Art
In recent years, storage devices using hard disks are becoming indispensable in various fields such as personal computers, hard disk recorders, video cameras and mobile telephones. Depending on the fields applied, there are various specifications required of the storage devices using the hard disks. For example, high speed and large capacity are required of a hard disk mounted on a personal computer. In order to improve the high-speed performance and the large capacity, the error correction coding with high correction capability needs to be implemented. However, since the amount of data handled per unit time increases as the high-speed performance advances, the error per unit time increase proportionally.
Thus, reloading back into a hard disk takes places when an error correction method having a low error correction capability is used. This increases the access time, causing a bottleneck in achieving the high speed operation.
It is generally desired that a signal sequence whose DC components are reduced or eliminated be used as a signal sequence on which the error correction coding is to be performed. Hereinafter this will be referred to as “DC-free” or “DC-free property”. The DC-free means that the frequency is 0, that is, the spectrum in the DC components is 0. In other words, the ratio of 0's and 1's contained in a plurality of bits contained in a signal sequence before a modulation is the same or the like. With a signal sequence provided with the DC-free property, the average level of a reproduced signal obtained from a recording pattern of modulation data stored in the storage medium is constantly fixed within a range of a predetermined signal sequence length. This property contributes to enhancing the noise tolerance. That is, in a signal sequence having a low DC-free property, the detection probability will be low in the detection of data using a Viterbi algorithm. As a result, the correction capability in low-density parity check decoding or Reed-Solomon decoding will be also reduced. In general, run-length limited codes are used in order to ensure the synchronism between the sampling timing and the data. The run-length limited code is a coding where the maximum length of consecutive 0's and the maximum length of consecutive 1's are restricted.
Conventionally, a method is proposed, as a run-length limited coding method, where while the DC-free property is met, the run-length limited coding is performed on a signal sequence with different redundancy bits affixed and a sequence having a characteristic closer to the DC-free is selected from among a plurality of coded sequences (See Patent Document 1, for instance). Also, proposed is a method where a run-length limited coding having a plurality of different properties is executed and a sequence having a characteristic closer to the DC-free is selected from among a plurality of coded sequences (See Patent Document 2, for instance).
[Patent Document 1] Japanese Patent Application Laid-Open No. 2002-100125.
[Patent Document 2] Japanese Patent Application Laid-Open No. 2004-213863.
Under these circumstances, the inventors of the present invention had come to recognize the following problems to be resolved. When the DC-free coding is to be accomplished by selecting sequences having a satisfactory DC-free property from among a plurality of coded sequences, there are cases where in a plurality of coded sequences to be selected there is no coded sequences having a satisfactory DC-free property. That is, there is a problem where a structure is required such that at least one sequence having the satisfactory DC-free property and this required structure affects the circuit scale and storage capacity.